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In previous columns, I have discussed matched length routing and how matched length does not necessarily mean matched delay. But, all design rules, specified by chip manufacturers regarding high-speed routing, specify matched length--not matched delay. In this month’s column we’ll take a look at the actual differences between the two.
Typically, more than one layer change is required when routing traces to matched length. Figure 1 illustrates the DDR2 address bus routing I did in Altium Designer, my preferred layout tool. In this case, each address signal has four layer changes. The red and green traces are the top and bottom layers--which should be kept as short as possible--and the yellow and orange traces are inner layers embedded between the planes. This was a particularly difficult route as there were two DDR2 memory chips placed on both the top and bottom sides of the board, so each address signal had to go to four different chips and still maintain the correct delay.
Figure 1: Matched delay T-section DDR2 address routing in Altium Designer.
The longest routes should be placed on the inner layers as this reduces electromagnetic radiation. With all other factors being equal, generally, a trace routed on the inner stripline layer exhibits 4-10 dB less noise than a trace routed on the outer microstrip layer. Also, please note that there are more high harmonics on the top layer routing. The high-frequency components radiate more readily because their shorter wavelengths are comparable to trace lengths, which act as antennas. Consequently, although the amplitude of the harmonic frequency components decreases as the frequency increases, the radiated frequency varies depending on the trace’s characteristics.
Read the full column here.
Editor's Note: This column originally appeared in the March 2014 issue of The PCB Design Magazine.