Quiet Power: Be Aware of Default Values in Circuit Simulators

Simulators are very convenient for getting quick answers without lengthy, expensive, and time-consuming measurements. Simulators range from simple spreadsheet-based illustration tools[1] to very sophisticated 3D field solvers[2]. Somewhere in the middle, we have the generic circuit simulators—the most well-known among them being SPICE. Berkeley SPICE has been the grand-daddy of all SPICE tools[3], and these days, there are many professional SPICE variants available. These tools have been around for a long time, and we usually take the validity of their output for granted. While the tools may be bug-free, no tool can give us perfect answers for just any arbitrary numerical input; sometimes, we can be surprised if we forget about the numerical limits and the limitations imposed by internal default values.

As an example, I will show a few simulation results on a simple ladder-like power distribution network, all done with the free LTspice simulator [4] from Linear Technologies, now part of Analog Devices.
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Figure 1: LTspice schematics of a simple PDN.

Figure 1 shows the schematic diagram of a simplified ladder model of a point-of-load power distribution network (PDN). The PDN is represented by four cascaded blocks. On the left is an ideal voltage source with series resistance and inductance modeling the DC source. To its right is a PI model of the PCB with plane resistance and inductance, as well as bulk and ceramic capacitors. 

The next block describes the package with its series resistance, inductance, and capacitance. The 10-µF capacitance value suggests that this is not only the static capacitance of the package planes, but it also represents package capacitors. The last block on the right describes the die with a series RL term, a parallel capacitance, and a parallel load resistance, which is determined by the nominal voltage and the average power consumption. 

Outside of these blocks is a 1A AC current source injecting test current into the silicon node. Since all elements are linear and time-invariant models, the actual current value does not matter, but the 1A value is convenient because the simulated V (load) output voltage directly gives us impedance without the need for further scaling.
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Figure 2: Impedance magnitude and phase of the simple PDN shown in Figure 1.

Figure 2 shows the result. The heavier line is the impedance magnitude with its scale on the left, the phase is the thin line with its scale on the right. We see four resonance peaks and one sharp dip on the plot. Peaks 1, 2, and 3 come from the anti-resonances of neighboring capacitor banks. For instance, the first peak is formed by Lsrc and Cbulk, and the LC parallel resonance of the 100-nH and 10000-µF values produce the 5-kHz resonance peak. To find the second peak, which comes from the series inductance of the Cbulk capacitor and the capacitance of Cceramic, we need to know the assumed inductance of Cbulk. 

You will notice that there are no series resistance and inductance symbols in series to the capacitors, so does it mean the simulation assumes zero values for those parasitics? In this regard, LTspice is unique among the SPICE circuit simulators. We can specify the usual simple parasitics without adding the corresponding schematic elements. 
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Figure 3: Screenshot explaining the capacitor equivalent circuit in LTspice.

The equivalent circuit, as defined in LT Wiki[5], is shown in Figure 3. We can specify not only the equivalent series resistance and inductance but also two parallel loss elements and a body capacitance. These parameters will be frequency-independent entries. But how do we enter these parameters if we don’t want to type up the SPICE deck manually? 
 
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Figure 4: Options to enter parasitic values for capacitors in LTspice.

LTspice makes it easy, offering multiple options. In Figure 4, the left portion shows what happens if we move the cursor over a capacitor in the schematic diagram and right-click. A window pops up where we can manually enter various attributes. On the right, you see the window which pops up when you hold the control key while you right-click. The two windows offer somewhat different choices. On the left—in addition to the equivalent series resistance, inductance, and body capacitance—we have only one parallel resistance entry. On the right, we can enter every parameter listed in Figure 3, including the initial condition, temperature, and the multiplier (m or x), which is a convenient way to simplify the schematics if we have m number of identical capacitors connected in parallel. We can also hide parameters or make them visible on the schematic using the checkmark in the last column. For the schematics shown, I turned on the feature only for the capacitance value; otherwise, the view would become very crowded. Notice that I show the actual parasitic values that were used to generate figure 2. Now, we see that the series inductance of the bulk capacitor is 10 nH, and this creates the anti-resonance with the 100-µF ceramic capacitor. From these two values, we get a 150-kHz antiresonance frequency, and that is exactly where Peak 2 is. Peak 3 is at 150 MHz, and it appears to be split by the sharp and deep Notch 4.
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Table 1: Parasitic values of capacitors that were used to generate Figure 2.

Table 1 summarizes the capacitor-parasitic values for all four capacitors. We may wonder if the values in this table represent reality because ESR and ESL for the ceramic capacitor appear to be unrealistically low. Yes, it would be unrealistic to expect these values from a single capacitor, but if we imagine that these values represent ten pieces of 10-µF ceramic capacitor with 5-mOhm ESR and 1-nH ESL in each, then it looks reasonable.

If we move on to look at the resonance at Peak 3, we realize that it is formed by the 10-nF Cdie capacitance and the equivalent inductance of the entire network looking back from the silicon, which is the well-known die-package resonance. By the time we properly add up all series and parallel inductances, it comes out around 160 pH. The antiresonance with the 10-nF Cdie value comes out close to 100 MHz, where the split antiresonance peak happens. 
 
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Figure 5: Impedance magnitude and phase of the simple PDN showed in Figure 1, but all parallel body capacitance is set to zero.

We still need to understand where the two extra resonances—Notch 4 and Peak 5—come from. To get the answer, we need to go back to Figure 4 and check what happens with the parameters that we did not fill out. On the left, there are two parameters we left empty: parallel capacitance and parallel resistance. What happens if we explicitly set the body capacitance to zero? The result is shown in Figure 5. Notch 4 and Peak 5 disappeared, but the rest remained practically unchanged. 
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Figure 6: Equivalent circuit of inductor parasitics and attribute list.

Now, the resonance pattern makes sense, but there is still something happening. Why do we have 5-mOhm impedance at low frequencies, when the circuit calls out only 1 mOhm and three times 0.1-mOhm resistor values in the series path, altogether 1.3-mOhm series resistance? We need to look at the definitions of the inductors. The definition of inductor attributes is shown in Figure 6[5].

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Figure 7: Parasitic definitions of the Lsrc inductor.

In the same way we did it for the capacitors, we can call up the parameter-entry windows for the inductors as well. In Figure 7, we see two parasitic components listed: series resistance and parallel capacitance. We also see a note at the bottom of the left window. There is a 1-mOhm default value for the series resistance. This means if we do not make an entry there, the tool will automatically add a 1-mOhm value (but this automatically-added value does not show up in the series resistance input field). This explains the low-frequency value in Figure 2 since we have four series inductors, each will have 1-mOhm series resistance by default. 
novak_fig8_0820.jpg
Figure 8: Impedance magnitude and phase of the simple PDN showed in Figure 1, with forcing zero body capacitance of capacitors and zero series resistance of inductors.

If we explicitly call out zero for the series resistance parasitics on all inductors, we get Figure 8. Now, the low-frequency value starts at the correct 1.3-mOhm value, but we can also notice that the first two peaks get a little bigger. This is happening because we removed the extra series resistances, which helped to lower the antiresonance peaks. Note that with the circuit values used in this example, explicitly calling out zero body capacitance for the inductors will not change the result.

This is eventually what we expect: a smooth impedance profile, no unexpected and unexplained sharp resonances, and asymptotic low-frequency impedance matches the sum of series resistance values. 
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Figure 9: Checking the body capacitance default value for the capacitor model.

We are almost done, but it still would be useful to check the capacitor’s equivalent circuit one more time and take another look at the body capacitance. To make it simple, we look at a single capacitor, as shown in Figure 9. We set the main capacitance as a parameter so that we can step it and set the ESR and ESL to fixed values—10 mOhm and 1 nH, respectively. To see what happens, we intentionally do not specify the parallel body capacitance; the entry is left blank. 

We step the capacitance from 1 pF to 1F in four large logarithmic steps and sweep the frequency from 1 mHz to 1 THz. The result shows that, in fact, a parallel body capacitance is added by the simulator, but its value is not fixed; it depends on the other parameters. With the values used here, the body capacitance seems to be approximately one million times smaller than the main capacitance. While this looks like a huge ratio (and it is), we see that if we simulate our circuit over many decades of frequencies, this small default body capacitance value still can cause unexpected artifacts. The good news is that it is easy to deal with; we just have to remember to call out specifically zero body capacitance, unless, of course, when we know its correct value and want to simulate the effect of the body capacitance.

And a final note: Remember that all numerical tools have to set limits for the input numbers they can accept and process, whether the tools will tell you and remind you. Next time, when you see unexpected things in circuit-simulation results, first make sure that the input numbers, including potential defaults, are set correctly.  

References 
1. Parallel Impedance of Four Groups of Capacitors.
2. High-Frequency Structure Simulator.
3. Berkeley SPICE.
4. LTspice.
5. LTwiki.

This column originally appeared in the August 2020 issue of Design007 Magazine.

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2020

Quiet Power: Be Aware of Default Values in Circuit Simulators

08-27-2020

Simulators are very convenient for getting quick answers without lengthy, expensive, and time-consuming measurements. Istvan Novak explains how, sometimes, you can be surprised if you forget about the numerical limits and the limitations imposed by internal default values.

View Story

Quiet Power: Do You Really Need That Ferrite Bead in the PDN?

07-30-2020

Many times, users have to rely on application notes from chip vendors to figure out how to design the PDN for the active device. Within this still vast area of application notes, Istvan Novak focuses on just one question that greatly divides even the experts: Is it okay, necessary, or harmful to use ferrite beads in the PDN?

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Quiet Power: PCB Fixtures for Power Integrity

02-15-2020

Power-integrity components—such as bypass capacitors, inductors, ferrite beads, or other small discrete components—can be characterized in fixtures. Istvan Novak discusses the wide range of PCB fixtures available for power integrity.

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2019

Quiet Power: How Much Signal Do We Lose Due to Reflections?

11-18-2019

We know that in the signal integrity world, reflections are usually bad. In clock networks, reflection glitches may cause multiple and false clock triggering. In medium-speed digital signaling, reflections will reduce noise margin, and in high-speed serializer/deserializer (SerDes) signaling, reflections increase jitter and create vertical eye closure.

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2018

Quiet Power: Measurement-to-Simulation Correlation on Thin Laminate Test Boards

12-19-2018

A year ago, I introduced causal and frequency-dependent simulation program with integrated circuit emphasis (SPICE) grid models for simulating power-ground plane impedance. The idea behind the solution was to calculate the actual R, L, G, and C parameters for each of the plane segments separately at every frequency point, run a single-point AC simulation, and then stitch the data together to get the frequency-dependent AC response. This month, I will demonstrate how that simple model correlates to measured data and simulation results from other tools.

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2017

Quiet Power: Causal Power Plane Models

12-13-2017

Causal and frequency-dependent models and simulations are important for today’s high-speed signal integrity simulations. But are causal models also necessary for power integrity simulations? When we do signal integrity eye diagram simulations, we define the source signals, so if we use the correct causal models for the passive channel, we will get the correct waveforms and eye reduction due to distortions on the main path and noise contributions from the coupling paths. Istvan Novak explains.

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2016

Dynamic Models for Passive Components

05-11-2016

A year ago, my Quiet Power column described the possible large loss of capacitance in multilayer ceramic capacitors (MLCC) when DC bias voltage is applied. However, DC bias effect is not the only way we can lose capacitance. Temperature, aging, and the magnitude of the AC voltage across the ceramic capacitor also can change its capacitance.

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2015

Avoid Overload in Gain-Phase Measurements

07-01-2015

There is a well-established theory to design stable control loops, but in the case of power converters, we face a significant challenge: each application may require a different set of output capacitors coming with our loads. Since the regulation feedback loop goes through our bypass capacitors, our application-dependent set of capacitors now become part of the control feedback loop. Unfortunately, certain combination of output capacitors may cause the converter to become unstable, something we want to avoid. This raises the need to test, measure, or simulate the control-loop stability. Istvan Novak has more.

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Effects of DC Bias on Ceramic Capacitors

04-01-2015

The density of multilayer ceramic capacitors has increased tremendously over the years. While 15 years ago a state-of-the-art X5R 10V 0402 (EIA) size capacitor might have had a maximum capacitance of 0.1 uF, today the same size capacitor may be available with 10 uF capacitance. This huge increase in density unfortunately comes with a very ugly downside. Istvan Novak has more.

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2014

Vertical Resonances in Ceramic Capacitors

12-03-2014

Because of their small size, we might think that structural resonances inside the ceramic capacitors do not exist in the frequency range where we usually care for the PDN. The unexpected fact is that the better PDN we try to make, the higher the chances that structural resonances inside ceramic capacitors do show up. This column tells you why and how.

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Quiet Power: Vertical Resonances in Ceramic Capacitors

12-03-2014

Because of their small size, we might think that structural resonances inside the ceramic capacitors do not exist in the frequency range where we usually care for the PDN. The unexpected fact is that the better PDN we try to make, the higher the chances that structural resonances inside ceramic capacitors do show up. This column tells you why and how.

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Checking Cable Performance with VNA

04-02-2014

In a previous column, Columnist Istvan Novak showed that poor cable shields can result in significant noise pickup from the air, which can easily mask a few mV of noise voltage needed to measure on a good power distribution rail. In this column, he looks at the same cables in the frequency domain, using a pocket-size vector network analyzer (VNA).

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Quiet Power: Checking Cable Performance with VNA

04-02-2014

In a previous column, Columnist Istvan Novak showed that poor cable shields can result in significant noise pickup from the air, which can easily mask a few mV of noise voltage needed to measure on a good power distribution rail. In this column, he looks at the same cables in the frequency domain, using a pocket-size vector network analyzer (VNA).

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Comparing Cable Shields

01-08-2014

In his last column, Istvan Novak looked at the importance of properly terminating cables even at low frequencies and also showed how much detail can be lost in PDN measurements when bad-quality cables are used. This month, he analyzes a step further the shield in cables.

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2013

Quiet Power: Cable Quality Matters

11-20-2013

In his August column Istvan Novak looked at the importance of properly terminating the cables that connect a measuring instrument to a device under test. He writes that we may be surprised to learn that even if the correct termination is used at the end of the cable, the measured waveform may depend on the quality of the cable used.

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Quiet Power: Don't Forget to Terminate Cables

10-23-2013

In high-speed signal integrity measurements, the first rule is to properly terminate traces and cables. However, many PDN measurements may be limited to lower frequencies, such as measuring the switching ripple of a DC-DC converter. Do you really need to terminate measurement cables if the signal you want to measure is the switching ripple of a converter running at 1 MHz?

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Quiet Power: Do Not Measure PDN Noise Across Capacitors!

08-07-2013

PDN noise can be measured in a variety of ways, but measuring across a capacitor will attenuate the high-frequency burst noise. Keep in mind that by measuring across a capacitor, the converter output ripple reading could be several times higher--or many times smaller--than the actual ripple across our loads.

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Quiet Power: How to Read the ESR Curve

01-15-2013

To use bypass capacitors properly, any designer must understand ESR (effective series resistance). A designer must understand what it means and how to read the ESR curve in measured or simulated plots.

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2012

Quiet Power: What's the Best Method for Probing a PDN?

08-15-2012

Recently, one of Istvan Novak's friends asked him about the preferred method of probing a power distribution network: "Which probe should I use to measure power plane noise?" Although, as usual, the correct answer begins with "It depends," in this case the generic answer is more clear-cut: For many PDN measurements, a simple passive coaxial cable is better.

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Quiet Power: Will Power Planes Disappear?

04-04-2012

Istvan Novak takes a look at an award-winning paper presented at DesignCon 2012, and he discusses the apparent disappearance of power planes from PCBs. In the future, the need for power planes may diminish or go away altogether. The change is already under way, and power planes, full-layer planes in particular, are disappearing fast from printed circuit boards.

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Do Bypass Capacitors Change Plane Resonances?

02-01-2012

My friend Greg recently asked me, "If I add surface-mount capacitors to a bare pair of planes, I am told that the resonant frequency will drop. On the other hand, someone with expertise is telling me that this is not the case. What would you expect to see?" As happens many times, both observations have elements of the truth in them, and a third scenario is not out of the question.

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2011

Be Careful with Transmission Lines in Plane Models

11-16-2011

Last month, we learned how we can determine the grid equivalent circuit parameters for a plane pair. You may wonder: Is it better to use LC lumped components in the SPICE netlist or to make use of SPICE's built-in transmission line models? In short, we can use either of them, but we need to set up our models and expectations correctly.

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Quiet Power: Simulating Planes with SPICE

10-12-2011

There are several excellent commercial tools available for simulating power distribution planes. However, you don't need a commercial tool to do simple plane analysis. You can, for instance, write your SPICE input file and use the free Berkeley SPICE engine to get result. If you want to do your own plane simulations, there are a couple of simple choice.

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Quiet Power: Does Dk Matter for Power Distribution?

08-16-2011

We know that in signal integrity, the relative dielectric constant (Dk) of the laminate is important. Dk sets the delay of traces, the characteristic impedance of interconnects and also scales the static capacitance of structures. Is the same true for power distribution? The answer is yes, but for power distribution all this matters much less.

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2010

Do Not Perforate Planes Unnecessarily

11-03-2010

For this column, I will take a quick detour from the series on the inductance of bypass capacitors. I will devote this column to a few comments about via placement and its potentially detrimental impact on signal and power integrity when antipads heavily perforate planes.

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Inductance of Bypass Capacitors, Part III

08-18-2010

In Part III of a series, we'll take a look at loop or mounted inductance. Loop inductance is important, for instance, when we need a reasonably accurate estimate for the Series Resonance Frequency (SRF), or for the anti-resonance peaking between two different-valued capacitors or between the capacitor's inductance and the static capacitance of the power/ground planes it connects to.

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Quiet Power: Inductance of Bypass Capacitors, Part II

07-21-2010

We finished the last Quiet Power column with a few questions about the inductance of bypass capacitors: Why do different vendors sometimes report different inductance values for nominally the same capacitor? Start by asking the vendors how they obtained these inductance values.

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Why PI Design is More Difficult Than SI

05-19-2010

Why is power integrity design more difficult than signal integrity design? Reasons abound, and unlike SI, we've only begun to study PI. Collective wisdom and experience gained over the coming years will help to alleviate the pain somewhat, but we should expect the challenge to stay with us for some time.

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Why S11 VNA Measurements Don't Work for PDN Measurements

04-14-2010

In this edition of Quiet Power, Istvan Novak continues to examine one-port and two-port vector network analyzer set-ups for PDN measurements, and other tricks and techniques for measuring impedance values below 5 milliohms.

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PDN Measurements: Reducing Cable-Braid Loop Error

02-24-2010

At low and mid frequencies, where the self-impedance of a DUT may reach milliohm values, a fundamental challenge in measurement is the connection to the DUT. Unless we measure a single component in a well-constructed fixture, the homemade connections from the instrument to the DUT will introduce too much error. What's the solution? By Istvan Novak.

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Quiet Power: Calculating Basic Resonances in the PDN

01-27-2010

In my last column, I showed that the piecewise linear Bode plots of various PDN components can create peaking at some interim frequencies. Today, I must cover peaking in more detail, because, even today, certain articles, books and CAD tools provide the wrong answers to this problem.

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