Beyond Design: The Big Bang—Lumped Element to Distributed System

The simplistic approach to analyzing electronic circuits is to use the lumped element model. This methodology assumes that the attributes of the circuit—resistance, capacitance, and inductance—are concentrated into idealized electrical components connected by a network of perfectly conducting wires. However, in reality, that is not the case.

As the frequency and rise time increase, these elements become distributed continuously through the substrate along the entire length of the trace. The copper trace and the adjacent dielectric materials become a transmission line, the skin effect forces current into the outer regions of the conductor, and frequency-dependent losses impact on the quality of the signal. The PCB trace now behaves as a distributed system with parasitic inductance and capacitance characterized by delay and scattered reflections. The behavior we are now concerned about occurs in the frequency domain. In this month’s column, I will discuss the difference between the lumped element model and the distributed system. (Fig. 1)

olney-fig1-1219.jpg

In my previous column, “The Frequency Domain,” we saw that impedance is defined in both the time and frequency domains. In the time domain, the impedance of a resistor (R) can be represented by a relationship between voltage and current (Ohm’s Law). Similarly, an ideal capacitor (C) has a relationship between the stored charge and the voltage across its plates. And the behavior of an ideal inductor (L) is defined by how fast the current traveling through it changes in the time domain.

We group these three elements (RLC) in a category called lumped circuit elements, in the sense that their properties can be lumped into a single point. This is quite different from the properties of an ideal transmission line, which also consists of these three elements, but they are distributed continuously through the dielectric materials along its length. The distributed model is used when the wavelength be-comes comparable to the physical dimensions of the circuit, making the lumped model inaccurate. This typically occurs at high frequencies, where the wavelength is very short. How-ever, it can also occur on very long, low-frequency transmission lines, such as high-volt-age power lines. The three primary elements now include distributed capacitance, inductance, and conductance (G).

The lumped element model completely fails at one-quarter wavelength (a 90° phase change), with not only the value but the very nature of the component itself being unpredictable. Due to this wavelength dependency, the distributed system model is used mostly at higher frequencies.

It is important to realize that the terms lumped and distributed are not properties of the system itself. These properties are related to the size of the circuit, compared to the wavelength of the voltages and currents passing through it. So, a resistor is, or isn’t, a lumped element (even though it is usually meant to be one), depending on the frequency of the applied signals.

Lumped systems are described by ordinary differential equations because, due to the small size of the system (compared to the wavelength), the spatial derivatives can be neglected and we only need to consider time derivatives. On the other hand, for distributed systems, we need to take electromagnetic wave propagation into account to get spatial as well as time derivatives, which leads to partial differential equations in the frequency domain.

To read this entire column, which appeared in the December 2019 issue of Design007 Magazine, click here, or download the PDF to your library for further reference.

Back

2020

Beyond Design: The Big Bang—Lumped Element to Distributed System

01-24-2020

The simplistic approach to analyzing electronic circuits is to use the lumped element model. However, in reality, that is not the case. Barry Olney discusses the difference between the lumped element model and the distributed system.

View Story

Beyond Design: The Frequency Domain

01-02-2020

As system performance requirements increase, the PCB designer’s challenges become more complex. The impact of lower core voltages, higher frequencies, and faster edge rates has forced us into the frequency domain. At first, signal integrity can look quite daunting, but if we take the time to absorb the key concepts, then it is like visualizing a multilayer PCB from a different perspective. In this month’s column, Barry Olney looks at the frequency domain.

View Story
Back

2019

Beyond Design: The Big Bang—Lumped Element to Distributed System

01-24-2020

The simplistic approach to analyzing electronic circuits is to use the lumped element model. However, in reality, that is not the case. Barry Olney discusses the difference between the lumped element model and the distributed system.

View Story

Beyond Design: The Frequency Domain

01-02-2020

As system performance requirements increase, the PCB designer’s challenges become more complex. The impact of lower core voltages, higher frequencies, and faster edge rates has forced us into the frequency domain. At first, signal integrity can look quite daunting, but if we take the time to absorb the key concepts, then it is like visualizing a multilayer PCB from a different perspective. In this month’s column, Barry Olney looks at the frequency domain.

View Story
Back

2018

Beyond Design: 10 Fundamental Rules of High-speed PCB Design, Part 3

12-13-2018

Planes are essential in today’s high-speed multilayer PCBs. Unfortunately, the number of power supplies required is increasing dramatically with IC complexity. Now, accounting for them all has become a real challenge. The high number of supplies generally leads to higher layer count substrates. In the past, we used to have more signal routing layers than planes; the opposite is now the case when the majority of stackup layers are reserved for power distribution. Although this increases the cost, it may be a godsend because it provides segregation of critical signals to avoid crosstalk and reduces radiation.

View Story

10 Fundamental Rules of High-speed PCB Design, Pt. 2

11-15-2018

In last month’s column, I introduced the 10 fundamental rules of high-speed PCB design. The first rule was to establish design constraints before commencing the design. This prime strategy sets constraints upfront based on pre-layout analyses or recommendations and guidelines and is integral to the design flow to maintain the established requirements. This month, I will elaborate on the importance of controlling the impedance and floor planning the placement based on connectivity.

View Story

Beyond Design: It’s a Material World

09-10-2018

Years ago, when clock frequencies were low and signal rise times were slow, selecting a dielectric material for your PCB was not difficult; we all just used FR-4. And we didn’t really care about the properties of the materials. However, with today’s multi-gigabit designs and their extremely fast rise times and tight margins, precise material selection is crucial to the performance of the product. Materials used for the fabrication of the multilayer PCB absorb high frequencies and reduce edge rates, and that loss in the transmission lines is a major cause of signal integrity issues. But we are not all designing cutting-edge boards and sometimes we tend to over-specify requirements that can lead to inflated production costs.

View Story

Beyond Design: Crosstalk Margins

08-22-2018

What is an acceptable level of crosstalk? That depends on the technology being used, and this level has changed quite dramatically over the years, going from TTL logic devices to today’s high-speed Gbps devices. In this month’s column, I will delve into the threshold of acceptable crosstalk and how to mitigate its impact on high-speed designs.

View Story

10 Fundamental Rules of High-Speed PCB Design, Pt. 1

08-06-2018

Over the years, I have focused on high-speed design, signal and power integrity, and EMC design techniques in a plethora of published technical articles—all of which have key points to consider and present a tremendous amount of information to absorb. In my next few columns, I will elaborate on ten of the most important considerations to embrace to achieve successful high-speed PCB designs that perform reliably to expectations.

View Story

DDR3/4 Fly-by Topology Termination and Routing

07-18-2018

DDR3/4 fly-by topology is similar to daisy chain or multi-drop topology, but it includes very short stubs to each memory device in the chain to reduce the reflections. The advantage of fly-by topology is that it supports higher-frequency operation and improves signal integrity and timing on heavily loaded signals. If you are employing high-frequency DDR4, then the bandwidth of the channel needs to be as high as possible. However, with today’s extremely fast edge rates, the sequencing of the stubs and the end termination, and the associate load, can make a measurable difference in signal quality. In this month’s column I will look at how best to route DDR3/4 fly-by topology.

View Story

Beyond Design: Common Symptoms of Common-Mode Radiation

06-27-2018

Electromagnetic radiation from digital circuits can occur as either differential mode or common mode. Differential mode is typically equal and opposite and therefore any radiating fields will cancel. Conversely, common-mode radiation from two coupled conductors is identical. It does not cancel, but rather reinforces.

View Story

Beyond Design: A Review of HyperLynx DRC

05-30-2018

There is an old saying, “You get what you pay for.” Does this mean that you should not expect too much from free software? After all, free software usually comes at a price: the results might be inaccurate, the software might be time-consuming to set up and use, and the tool might overlook issues that require a revision to mitigate. But HyperLynx DRC is the exception to the rule.

View Story

Beyond Design: AC/DC is Not Just a Rock Band

04-27-2018

Positioned at our usual table at the local pub in Melbourne, Australia one night in 1972, the boys and I laughed as a school boy, guitarist Angus Young, set up equipment and tuned a guitar. We assumed he was one of the roadies, and were gobsmacked when AC/DC unexpectedly fired up. This month, I will discuss AC coupling (or is it DC blocking?) of high-speed serial links as my taste in music has matured over the years.

View Story

The Target Impedance Approach to PDN Design

03-13-2018

Before you worry (or not) about post-layout PDN DC drop analysis, you first need to design an effective PDN pre-layout. Smart designers prevent problems before they arise, while others waste time and resources trying to fix the mess that they inadvertently created due to their lack of due diligence. Engineers and PCB designers need to visualize and understand how and where the currents flow.

View Story
Back

2017

Beyond Design: 10 Fundamental Rules of High-speed PCB Design, Part 3

12-13-2018

Planes are essential in today’s high-speed multilayer PCBs. Unfortunately, the number of power supplies required is increasing dramatically with IC complexity. Now, accounting for them all has become a real challenge. The high number of supplies generally leads to higher layer count substrates. In the past, we used to have more signal routing layers than planes; the opposite is now the case when the majority of stackup layers are reserved for power distribution. Although this increases the cost, it may be a godsend because it provides segregation of critical signals to avoid crosstalk and reduces radiation.

View Story

10 Fundamental Rules of High-speed PCB Design, Pt. 2

11-15-2018

In last month’s column, I introduced the 10 fundamental rules of high-speed PCB design. The first rule was to establish design constraints before commencing the design. This prime strategy sets constraints upfront based on pre-layout analyses or recommendations and guidelines and is integral to the design flow to maintain the established requirements. This month, I will elaborate on the importance of controlling the impedance and floor planning the placement based on connectivity.

View Story

Beyond Design: It’s a Material World

09-10-2018

Years ago, when clock frequencies were low and signal rise times were slow, selecting a dielectric material for your PCB was not difficult; we all just used FR-4. And we didn’t really care about the properties of the materials. However, with today’s multi-gigabit designs and their extremely fast rise times and tight margins, precise material selection is crucial to the performance of the product. Materials used for the fabrication of the multilayer PCB absorb high frequencies and reduce edge rates, and that loss in the transmission lines is a major cause of signal integrity issues. But we are not all designing cutting-edge boards and sometimes we tend to over-specify requirements that can lead to inflated production costs.

View Story

Beyond Design: Crosstalk Margins

08-22-2018

What is an acceptable level of crosstalk? That depends on the technology being used, and this level has changed quite dramatically over the years, going from TTL logic devices to today’s high-speed Gbps devices. In this month’s column, I will delve into the threshold of acceptable crosstalk and how to mitigate its impact on high-speed designs.

View Story

10 Fundamental Rules of High-Speed PCB Design, Pt. 1

08-06-2018

Over the years, I have focused on high-speed design, signal and power integrity, and EMC design techniques in a plethora of published technical articles—all of which have key points to consider and present a tremendous amount of information to absorb. In my next few columns, I will elaborate on ten of the most important considerations to embrace to achieve successful high-speed PCB designs that perform reliably to expectations.

View Story

DDR3/4 Fly-by Topology Termination and Routing

07-18-2018

DDR3/4 fly-by topology is similar to daisy chain or multi-drop topology, but it includes very short stubs to each memory device in the chain to reduce the reflections. The advantage of fly-by topology is that it supports higher-frequency operation and improves signal integrity and timing on heavily loaded signals. If you are employing high-frequency DDR4, then the bandwidth of the channel needs to be as high as possible. However, with today’s extremely fast edge rates, the sequencing of the stubs and the end termination, and the associate load, can make a measurable difference in signal quality. In this month’s column I will look at how best to route DDR3/4 fly-by topology.

View Story

Beyond Design: Common Symptoms of Common-Mode Radiation

06-27-2018

Electromagnetic radiation from digital circuits can occur as either differential mode or common mode. Differential mode is typically equal and opposite and therefore any radiating fields will cancel. Conversely, common-mode radiation from two coupled conductors is identical. It does not cancel, but rather reinforces.

View Story

Beyond Design: A Review of HyperLynx DRC

05-30-2018

There is an old saying, “You get what you pay for.” Does this mean that you should not expect too much from free software? After all, free software usually comes at a price: the results might be inaccurate, the software might be time-consuming to set up and use, and the tool might overlook issues that require a revision to mitigate. But HyperLynx DRC is the exception to the rule.

View Story

Beyond Design: AC/DC is Not Just a Rock Band

04-27-2018

Positioned at our usual table at the local pub in Melbourne, Australia one night in 1972, the boys and I laughed as a school boy, guitarist Angus Young, set up equipment and tuned a guitar. We assumed he was one of the roadies, and were gobsmacked when AC/DC unexpectedly fired up. This month, I will discuss AC coupling (or is it DC blocking?) of high-speed serial links as my taste in music has matured over the years.

View Story

The Target Impedance Approach to PDN Design

03-13-2018

Before you worry (or not) about post-layout PDN DC drop analysis, you first need to design an effective PDN pre-layout. Smart designers prevent problems before they arise, while others waste time and resources trying to fix the mess that they inadvertently created due to their lack of due diligence. Engineers and PCB designers need to visualize and understand how and where the currents flow.

View Story
Back

2016

Beyond Design: 10 Fundamental Rules of High-speed PCB Design, Part 3

12-13-2018

Planes are essential in today’s high-speed multilayer PCBs. Unfortunately, the number of power supplies required is increasing dramatically with IC complexity. Now, accounting for them all has become a real challenge. The high number of supplies generally leads to higher layer count substrates. In the past, we used to have more signal routing layers than planes; the opposite is now the case when the majority of stackup layers are reserved for power distribution. Although this increases the cost, it may be a godsend because it provides segregation of critical signals to avoid crosstalk and reduces radiation.

View Story

10 Fundamental Rules of High-speed PCB Design, Pt. 2

11-15-2018

In last month’s column, I introduced the 10 fundamental rules of high-speed PCB design. The first rule was to establish design constraints before commencing the design. This prime strategy sets constraints upfront based on pre-layout analyses or recommendations and guidelines and is integral to the design flow to maintain the established requirements. This month, I will elaborate on the importance of controlling the impedance and floor planning the placement based on connectivity.

View Story

Beyond Design: It’s a Material World

09-10-2018

Years ago, when clock frequencies were low and signal rise times were slow, selecting a dielectric material for your PCB was not difficult; we all just used FR-4. And we didn’t really care about the properties of the materials. However, with today’s multi-gigabit designs and their extremely fast rise times and tight margins, precise material selection is crucial to the performance of the product. Materials used for the fabrication of the multilayer PCB absorb high frequencies and reduce edge rates, and that loss in the transmission lines is a major cause of signal integrity issues. But we are not all designing cutting-edge boards and sometimes we tend to over-specify requirements that can lead to inflated production costs.

View Story

Beyond Design: Crosstalk Margins

08-22-2018

What is an acceptable level of crosstalk? That depends on the technology being used, and this level has changed quite dramatically over the years, going from TTL logic devices to today’s high-speed Gbps devices. In this month’s column, I will delve into the threshold of acceptable crosstalk and how to mitigate its impact on high-speed designs.

View Story

10 Fundamental Rules of High-Speed PCB Design, Pt. 1

08-06-2018

Over the years, I have focused on high-speed design, signal and power integrity, and EMC design techniques in a plethora of published technical articles—all of which have key points to consider and present a tremendous amount of information to absorb. In my next few columns, I will elaborate on ten of the most important considerations to embrace to achieve successful high-speed PCB designs that perform reliably to expectations.

View Story

DDR3/4 Fly-by Topology Termination and Routing

07-18-2018

DDR3/4 fly-by topology is similar to daisy chain or multi-drop topology, but it includes very short stubs to each memory device in the chain to reduce the reflections. The advantage of fly-by topology is that it supports higher-frequency operation and improves signal integrity and timing on heavily loaded signals. If you are employing high-frequency DDR4, then the bandwidth of the channel needs to be as high as possible. However, with today’s extremely fast edge rates, the sequencing of the stubs and the end termination, and the associate load, can make a measurable difference in signal quality. In this month’s column I will look at how best to route DDR3/4 fly-by topology.

View Story

Beyond Design: Common Symptoms of Common-Mode Radiation

06-27-2018

Electromagnetic radiation from digital circuits can occur as either differential mode or common mode. Differential mode is typically equal and opposite and therefore any radiating fields will cancel. Conversely, common-mode radiation from two coupled conductors is identical. It does not cancel, but rather reinforces.

View Story

Beyond Design: A Review of HyperLynx DRC

05-30-2018

There is an old saying, “You get what you pay for.” Does this mean that you should not expect too much from free software? After all, free software usually comes at a price: the results might be inaccurate, the software might be time-consuming to set up and use, and the tool might overlook issues that require a revision to mitigate. But HyperLynx DRC is the exception to the rule.

View Story

Beyond Design: AC/DC is Not Just a Rock Band

04-27-2018

Positioned at our usual table at the local pub in Melbourne, Australia one night in 1972, the boys and I laughed as a school boy, guitarist Angus Young, set up equipment and tuned a guitar. We assumed he was one of the roadies, and were gobsmacked when AC/DC unexpectedly fired up. This month, I will discuss AC coupling (or is it DC blocking?) of high-speed serial links as my taste in music has matured over the years.

View Story

The Target Impedance Approach to PDN Design

03-13-2018

Before you worry (or not) about post-layout PDN DC drop analysis, you first need to design an effective PDN pre-layout. Smart designers prevent problems before they arise, while others waste time and resources trying to fix the mess that they inadvertently created due to their lack of due diligence. Engineers and PCB designers need to visualize and understand how and where the currents flow.

View Story
Back

2015

Beyond Design: 10 Fundamental Rules of High-speed PCB Design, Part 3

12-13-2018

Planes are essential in today’s high-speed multilayer PCBs. Unfortunately, the number of power supplies required is increasing dramatically with IC complexity. Now, accounting for them all has become a real challenge. The high number of supplies generally leads to higher layer count substrates. In the past, we used to have more signal routing layers than planes; the opposite is now the case when the majority of stackup layers are reserved for power distribution. Although this increases the cost, it may be a godsend because it provides segregation of critical signals to avoid crosstalk and reduces radiation.

View Story

10 Fundamental Rules of High-speed PCB Design, Pt. 2

11-15-2018

In last month’s column, I introduced the 10 fundamental rules of high-speed PCB design. The first rule was to establish design constraints before commencing the design. This prime strategy sets constraints upfront based on pre-layout analyses or recommendations and guidelines and is integral to the design flow to maintain the established requirements. This month, I will elaborate on the importance of controlling the impedance and floor planning the placement based on connectivity.

View Story

Beyond Design: It’s a Material World

09-10-2018

Years ago, when clock frequencies were low and signal rise times were slow, selecting a dielectric material for your PCB was not difficult; we all just used FR-4. And we didn’t really care about the properties of the materials. However, with today’s multi-gigabit designs and their extremely fast rise times and tight margins, precise material selection is crucial to the performance of the product. Materials used for the fabrication of the multilayer PCB absorb high frequencies and reduce edge rates, and that loss in the transmission lines is a major cause of signal integrity issues. But we are not all designing cutting-edge boards and sometimes we tend to over-specify requirements that can lead to inflated production costs.

View Story

Beyond Design: Crosstalk Margins

08-22-2018

What is an acceptable level of crosstalk? That depends on the technology being used, and this level has changed quite dramatically over the years, going from TTL logic devices to today’s high-speed Gbps devices. In this month’s column, I will delve into the threshold of acceptable crosstalk and how to mitigate its impact on high-speed designs.

View Story

10 Fundamental Rules of High-Speed PCB Design, Pt. 1

08-06-2018

Over the years, I have focused on high-speed design, signal and power integrity, and EMC design techniques in a plethora of published technical articles—all of which have key points to consider and present a tremendous amount of information to absorb. In my next few columns, I will elaborate on ten of the most important considerations to embrace to achieve successful high-speed PCB designs that perform reliably to expectations.

View Story

DDR3/4 Fly-by Topology Termination and Routing

07-18-2018

DDR3/4 fly-by topology is similar to daisy chain or multi-drop topology, but it includes very short stubs to each memory device in the chain to reduce the reflections. The advantage of fly-by topology is that it supports higher-frequency operation and improves signal integrity and timing on heavily loaded signals. If you are employing high-frequency DDR4, then the bandwidth of the channel needs to be as high as possible. However, with today’s extremely fast edge rates, the sequencing of the stubs and the end termination, and the associate load, can make a measurable difference in signal quality. In this month’s column I will look at how best to route DDR3/4 fly-by topology.

View Story

Beyond Design: Common Symptoms of Common-Mode Radiation

06-27-2018

Electromagnetic radiation from digital circuits can occur as either differential mode or common mode. Differential mode is typically equal and opposite and therefore any radiating fields will cancel. Conversely, common-mode radiation from two coupled conductors is identical. It does not cancel, but rather reinforces.

View Story

Beyond Design: A Review of HyperLynx DRC

05-30-2018

There is an old saying, “You get what you pay for.” Does this mean that you should not expect too much from free software? After all, free software usually comes at a price: the results might be inaccurate, the software might be time-consuming to set up and use, and the tool might overlook issues that require a revision to mitigate. But HyperLynx DRC is the exception to the rule.

View Story

Beyond Design: AC/DC is Not Just a Rock Band

04-27-2018

Positioned at our usual table at the local pub in Melbourne, Australia one night in 1972, the boys and I laughed as a school boy, guitarist Angus Young, set up equipment and tuned a guitar. We assumed he was one of the roadies, and were gobsmacked when AC/DC unexpectedly fired up. This month, I will discuss AC coupling (or is it DC blocking?) of high-speed serial links as my taste in music has matured over the years.

View Story

The Target Impedance Approach to PDN Design

03-13-2018

Before you worry (or not) about post-layout PDN DC drop analysis, you first need to design an effective PDN pre-layout. Smart designers prevent problems before they arise, while others waste time and resources trying to fix the mess that they inadvertently created due to their lack of due diligence. Engineers and PCB designers need to visualize and understand how and where the currents flow.

View Story
Back

2014

Beyond Design: 10 Fundamental Rules of High-speed PCB Design, Part 3

12-13-2018

Planes are essential in today’s high-speed multilayer PCBs. Unfortunately, the number of power supplies required is increasing dramatically with IC complexity. Now, accounting for them all has become a real challenge. The high number of supplies generally leads to higher layer count substrates. In the past, we used to have more signal routing layers than planes; the opposite is now the case when the majority of stackup layers are reserved for power distribution. Although this increases the cost, it may be a godsend because it provides segregation of critical signals to avoid crosstalk and reduces radiation.

View Story

10 Fundamental Rules of High-speed PCB Design, Pt. 2

11-15-2018

In last month’s column, I introduced the 10 fundamental rules of high-speed PCB design. The first rule was to establish design constraints before commencing the design. This prime strategy sets constraints upfront based on pre-layout analyses or recommendations and guidelines and is integral to the design flow to maintain the established requirements. This month, I will elaborate on the importance of controlling the impedance and floor planning the placement based on connectivity.

View Story

Beyond Design: It’s a Material World

09-10-2018

Years ago, when clock frequencies were low and signal rise times were slow, selecting a dielectric material for your PCB was not difficult; we all just used FR-4. And we didn’t really care about the properties of the materials. However, with today’s multi-gigabit designs and their extremely fast rise times and tight margins, precise material selection is crucial to the performance of the product. Materials used for the fabrication of the multilayer PCB absorb high frequencies and reduce edge rates, and that loss in the transmission lines is a major cause of signal integrity issues. But we are not all designing cutting-edge boards and sometimes we tend to over-specify requirements that can lead to inflated production costs.

View Story

Beyond Design: Crosstalk Margins

08-22-2018

What is an acceptable level of crosstalk? That depends on the technology being used, and this level has changed quite dramatically over the years, going from TTL logic devices to today’s high-speed Gbps devices. In this month’s column, I will delve into the threshold of acceptable crosstalk and how to mitigate its impact on high-speed designs.

View Story

10 Fundamental Rules of High-Speed PCB Design, Pt. 1

08-06-2018

Over the years, I have focused on high-speed design, signal and power integrity, and EMC design techniques in a plethora of published technical articles—all of which have key points to consider and present a tremendous amount of information to absorb. In my next few columns, I will elaborate on ten of the most important considerations to embrace to achieve successful high-speed PCB designs that perform reliably to expectations.

View Story

DDR3/4 Fly-by Topology Termination and Routing

07-18-2018

DDR3/4 fly-by topology is similar to daisy chain or multi-drop topology, but it includes very short stubs to each memory device in the chain to reduce the reflections. The advantage of fly-by topology is that it supports higher-frequency operation and improves signal integrity and timing on heavily loaded signals. If you are employing high-frequency DDR4, then the bandwidth of the channel needs to be as high as possible. However, with today’s extremely fast edge rates, the sequencing of the stubs and the end termination, and the associate load, can make a measurable difference in signal quality. In this month’s column I will look at how best to route DDR3/4 fly-by topology.

View Story

Beyond Design: Common Symptoms of Common-Mode Radiation

06-27-2018

Electromagnetic radiation from digital circuits can occur as either differential mode or common mode. Differential mode is typically equal and opposite and therefore any radiating fields will cancel. Conversely, common-mode radiation from two coupled conductors is identical. It does not cancel, but rather reinforces.

View Story

Beyond Design: A Review of HyperLynx DRC

05-30-2018

There is an old saying, “You get what you pay for.” Does this mean that you should not expect too much from free software? After all, free software usually comes at a price: the results might be inaccurate, the software might be time-consuming to set up and use, and the tool might overlook issues that require a revision to mitigate. But HyperLynx DRC is the exception to the rule.

View Story

Beyond Design: AC/DC is Not Just a Rock Band

04-27-2018

Positioned at our usual table at the local pub in Melbourne, Australia one night in 1972, the boys and I laughed as a school boy, guitarist Angus Young, set up equipment and tuned a guitar. We assumed he was one of the roadies, and were gobsmacked when AC/DC unexpectedly fired up. This month, I will discuss AC coupling (or is it DC blocking?) of high-speed serial links as my taste in music has matured over the years.

View Story

The Target Impedance Approach to PDN Design

03-13-2018

Before you worry (or not) about post-layout PDN DC drop analysis, you first need to design an effective PDN pre-layout. Smart designers prevent problems before they arise, while others waste time and resources trying to fix the mess that they inadvertently created due to their lack of due diligence. Engineers and PCB designers need to visualize and understand how and where the currents flow.

View Story
Back

2013

Beyond Design: 10 Fundamental Rules of High-speed PCB Design, Part 3

12-13-2018

Planes are essential in today’s high-speed multilayer PCBs. Unfortunately, the number of power supplies required is increasing dramatically with IC complexity. Now, accounting for them all has become a real challenge. The high number of supplies generally leads to higher layer count substrates. In the past, we used to have more signal routing layers than planes; the opposite is now the case when the majority of stackup layers are reserved for power distribution. Although this increases the cost, it may be a godsend because it provides segregation of critical signals to avoid crosstalk and reduces radiation.

View Story

10 Fundamental Rules of High-speed PCB Design, Pt. 2

11-15-2018

In last month’s column, I introduced the 10 fundamental rules of high-speed PCB design. The first rule was to establish design constraints before commencing the design. This prime strategy sets constraints upfront based on pre-layout analyses or recommendations and guidelines and is integral to the design flow to maintain the established requirements. This month, I will elaborate on the importance of controlling the impedance and floor planning the placement based on connectivity.

View Story

Beyond Design: It’s a Material World

09-10-2018

Years ago, when clock frequencies were low and signal rise times were slow, selecting a dielectric material for your PCB was not difficult; we all just used FR-4. And we didn’t really care about the properties of the materials. However, with today’s multi-gigabit designs and their extremely fast rise times and tight margins, precise material selection is crucial to the performance of the product. Materials used for the fabrication of the multilayer PCB absorb high frequencies and reduce edge rates, and that loss in the transmission lines is a major cause of signal integrity issues. But we are not all designing cutting-edge boards and sometimes we tend to over-specify requirements that can lead to inflated production costs.

View Story

Beyond Design: Crosstalk Margins

08-22-2018

What is an acceptable level of crosstalk? That depends on the technology being used, and this level has changed quite dramatically over the years, going from TTL logic devices to today’s high-speed Gbps devices. In this month’s column, I will delve into the threshold of acceptable crosstalk and how to mitigate its impact on high-speed designs.

View Story

10 Fundamental Rules of High-Speed PCB Design, Pt. 1

08-06-2018

Over the years, I have focused on high-speed design, signal and power integrity, and EMC design techniques in a plethora of published technical articles—all of which have key points to consider and present a tremendous amount of information to absorb. In my next few columns, I will elaborate on ten of the most important considerations to embrace to achieve successful high-speed PCB designs that perform reliably to expectations.

View Story

DDR3/4 Fly-by Topology Termination and Routing

07-18-2018

DDR3/4 fly-by topology is similar to daisy chain or multi-drop topology, but it includes very short stubs to each memory device in the chain to reduce the reflections. The advantage of fly-by topology is that it supports higher-frequency operation and improves signal integrity and timing on heavily loaded signals. If you are employing high-frequency DDR4, then the bandwidth of the channel needs to be as high as possible. However, with today’s extremely fast edge rates, the sequencing of the stubs and the end termination, and the associate load, can make a measurable difference in signal quality. In this month’s column I will look at how best to route DDR3/4 fly-by topology.

View Story

Beyond Design: Common Symptoms of Common-Mode Radiation

06-27-2018

Electromagnetic radiation from digital circuits can occur as either differential mode or common mode. Differential mode is typically equal and opposite and therefore any radiating fields will cancel. Conversely, common-mode radiation from two coupled conductors is identical. It does not cancel, but rather reinforces.

View Story

Beyond Design: A Review of HyperLynx DRC

05-30-2018

There is an old saying, “You get what you pay for.” Does this mean that you should not expect too much from free software? After all, free software usually comes at a price: the results might be inaccurate, the software might be time-consuming to set up and use, and the tool might overlook issues that require a revision to mitigate. But HyperLynx DRC is the exception to the rule.

View Story

Beyond Design: AC/DC is Not Just a Rock Band

04-27-2018

Positioned at our usual table at the local pub in Melbourne, Australia one night in 1972, the boys and I laughed as a school boy, guitarist Angus Young, set up equipment and tuned a guitar. We assumed he was one of the roadies, and were gobsmacked when AC/DC unexpectedly fired up. This month, I will discuss AC coupling (or is it DC blocking?) of high-speed serial links as my taste in music has matured over the years.

View Story

The Target Impedance Approach to PDN Design

03-13-2018

Before you worry (or not) about post-layout PDN DC drop analysis, you first need to design an effective PDN pre-layout. Smart designers prevent problems before they arise, while others waste time and resources trying to fix the mess that they inadvertently created due to their lack of due diligence. Engineers and PCB designers need to visualize and understand how and where the currents flow.

View Story
Back

2012

Beyond Design: 10 Fundamental Rules of High-speed PCB Design, Part 3

12-13-2018

Planes are essential in today’s high-speed multilayer PCBs. Unfortunately, the number of power supplies required is increasing dramatically with IC complexity. Now, accounting for them all has become a real challenge. The high number of supplies generally leads to higher layer count substrates. In the past, we used to have more signal routing layers than planes; the opposite is now the case when the majority of stackup layers are reserved for power distribution. Although this increases the cost, it may be a godsend because it provides segregation of critical signals to avoid crosstalk and reduces radiation.

View Story

10 Fundamental Rules of High-speed PCB Design, Pt. 2

11-15-2018

In last month’s column, I introduced the 10 fundamental rules of high-speed PCB design. The first rule was to establish design constraints before commencing the design. This prime strategy sets constraints upfront based on pre-layout analyses or recommendations and guidelines and is integral to the design flow to maintain the established requirements. This month, I will elaborate on the importance of controlling the impedance and floor planning the placement based on connectivity.

View Story

Beyond Design: It’s a Material World

09-10-2018

Years ago, when clock frequencies were low and signal rise times were slow, selecting a dielectric material for your PCB was not difficult; we all just used FR-4. And we didn’t really care about the properties of the materials. However, with today’s multi-gigabit designs and their extremely fast rise times and tight margins, precise material selection is crucial to the performance of the product. Materials used for the fabrication of the multilayer PCB absorb high frequencies and reduce edge rates, and that loss in the transmission lines is a major cause of signal integrity issues. But we are not all designing cutting-edge boards and sometimes we tend to over-specify requirements that can lead to inflated production costs.

View Story

Beyond Design: Crosstalk Margins

08-22-2018

What is an acceptable level of crosstalk? That depends on the technology being used, and this level has changed quite dramatically over the years, going from TTL logic devices to today’s high-speed Gbps devices. In this month’s column, I will delve into the threshold of acceptable crosstalk and how to mitigate its impact on high-speed designs.

View Story

10 Fundamental Rules of High-Speed PCB Design, Pt. 1

08-06-2018

Over the years, I have focused on high-speed design, signal and power integrity, and EMC design techniques in a plethora of published technical articles—all of which have key points to consider and present a tremendous amount of information to absorb. In my next few columns, I will elaborate on ten of the most important considerations to embrace to achieve successful high-speed PCB designs that perform reliably to expectations.

View Story

DDR3/4 Fly-by Topology Termination and Routing

07-18-2018

DDR3/4 fly-by topology is similar to daisy chain or multi-drop topology, but it includes very short stubs to each memory device in the chain to reduce the reflections. The advantage of fly-by topology is that it supports higher-frequency operation and improves signal integrity and timing on heavily loaded signals. If you are employing high-frequency DDR4, then the bandwidth of the channel needs to be as high as possible. However, with today’s extremely fast edge rates, the sequencing of the stubs and the end termination, and the associate load, can make a measurable difference in signal quality. In this month’s column I will look at how best to route DDR3/4 fly-by topology.

View Story

Beyond Design: Common Symptoms of Common-Mode Radiation

06-27-2018

Electromagnetic radiation from digital circuits can occur as either differential mode or common mode. Differential mode is typically equal and opposite and therefore any radiating fields will cancel. Conversely, common-mode radiation from two coupled conductors is identical. It does not cancel, but rather reinforces.

View Story

Beyond Design: A Review of HyperLynx DRC

05-30-2018

There is an old saying, “You get what you pay for.” Does this mean that you should not expect too much from free software? After all, free software usually comes at a price: the results might be inaccurate, the software might be time-consuming to set up and use, and the tool might overlook issues that require a revision to mitigate. But HyperLynx DRC is the exception to the rule.

View Story

Beyond Design: AC/DC is Not Just a Rock Band

04-27-2018

Positioned at our usual table at the local pub in Melbourne, Australia one night in 1972, the boys and I laughed as a school boy, guitarist Angus Young, set up equipment and tuned a guitar. We assumed he was one of the roadies, and were gobsmacked when AC/DC unexpectedly fired up. This month, I will discuss AC coupling (or is it DC blocking?) of high-speed serial links as my taste in music has matured over the years.

View Story

The Target Impedance Approach to PDN Design

03-13-2018

Before you worry (or not) about post-layout PDN DC drop analysis, you first need to design an effective PDN pre-layout. Smart designers prevent problems before they arise, while others waste time and resources trying to fix the mess that they inadvertently created due to their lack of due diligence. Engineers and PCB designers need to visualize and understand how and where the currents flow.

View Story
Back

2011

Beyond Design: 10 Fundamental Rules of High-speed PCB Design, Part 3

12-13-2018

Planes are essential in today’s high-speed multilayer PCBs. Unfortunately, the number of power supplies required is increasing dramatically with IC complexity. Now, accounting for them all has become a real challenge. The high number of supplies generally leads to higher layer count substrates. In the past, we used to have more signal routing layers than planes; the opposite is now the case when the majority of stackup layers are reserved for power distribution. Although this increases the cost, it may be a godsend because it provides segregation of critical signals to avoid crosstalk and reduces radiation.

View Story

10 Fundamental Rules of High-speed PCB Design, Pt. 2

11-15-2018

In last month’s column, I introduced the 10 fundamental rules of high-speed PCB design. The first rule was to establish design constraints before commencing the design. This prime strategy sets constraints upfront based on pre-layout analyses or recommendations and guidelines and is integral to the design flow to maintain the established requirements. This month, I will elaborate on the importance of controlling the impedance and floor planning the placement based on connectivity.

View Story

Beyond Design: It’s a Material World

09-10-2018

Years ago, when clock frequencies were low and signal rise times were slow, selecting a dielectric material for your PCB was not difficult; we all just used FR-4. And we didn’t really care about the properties of the materials. However, with today’s multi-gigabit designs and their extremely fast rise times and tight margins, precise material selection is crucial to the performance of the product. Materials used for the fabrication of the multilayer PCB absorb high frequencies and reduce edge rates, and that loss in the transmission lines is a major cause of signal integrity issues. But we are not all designing cutting-edge boards and sometimes we tend to over-specify requirements that can lead to inflated production costs.

View Story

Beyond Design: Crosstalk Margins

08-22-2018

What is an acceptable level of crosstalk? That depends on the technology being used, and this level has changed quite dramatically over the years, going from TTL logic devices to today’s high-speed Gbps devices. In this month’s column, I will delve into the threshold of acceptable crosstalk and how to mitigate its impact on high-speed designs.

View Story

10 Fundamental Rules of High-Speed PCB Design, Pt. 1

08-06-2018

Over the years, I have focused on high-speed design, signal and power integrity, and EMC design techniques in a plethora of published technical articles—all of which have key points to consider and present a tremendous amount of information to absorb. In my next few columns, I will elaborate on ten of the most important considerations to embrace to achieve successful high-speed PCB designs that perform reliably to expectations.

View Story

DDR3/4 Fly-by Topology Termination and Routing

07-18-2018

DDR3/4 fly-by topology is similar to daisy chain or multi-drop topology, but it includes very short stubs to each memory device in the chain to reduce the reflections. The advantage of fly-by topology is that it supports higher-frequency operation and improves signal integrity and timing on heavily loaded signals. If you are employing high-frequency DDR4, then the bandwidth of the channel needs to be as high as possible. However, with today’s extremely fast edge rates, the sequencing of the stubs and the end termination, and the associate load, can make a measurable difference in signal quality. In this month’s column I will look at how best to route DDR3/4 fly-by topology.

View Story

Beyond Design: Common Symptoms of Common-Mode Radiation

06-27-2018

Electromagnetic radiation from digital circuits can occur as either differential mode or common mode. Differential mode is typically equal and opposite and therefore any radiating fields will cancel. Conversely, common-mode radiation from two coupled conductors is identical. It does not cancel, but rather reinforces.

View Story

Beyond Design: A Review of HyperLynx DRC

05-30-2018

There is an old saying, “You get what you pay for.” Does this mean that you should not expect too much from free software? After all, free software usually comes at a price: the results might be inaccurate, the software might be time-consuming to set up and use, and the tool might overlook issues that require a revision to mitigate. But HyperLynx DRC is the exception to the rule.

View Story

Beyond Design: AC/DC is Not Just a Rock Band

04-27-2018

Positioned at our usual table at the local pub in Melbourne, Australia one night in 1972, the boys and I laughed as a school boy, guitarist Angus Young, set up equipment and tuned a guitar. We assumed he was one of the roadies, and were gobsmacked when AC/DC unexpectedly fired up. This month, I will discuss AC coupling (or is it DC blocking?) of high-speed serial links as my taste in music has matured over the years.

View Story

The Target Impedance Approach to PDN Design

03-13-2018

Before you worry (or not) about post-layout PDN DC drop analysis, you first need to design an effective PDN pre-layout. Smart designers prevent problems before they arise, while others waste time and resources trying to fix the mess that they inadvertently created due to their lack of due diligence. Engineers and PCB designers need to visualize and understand how and where the currents flow.

View Story
Back

2010

Beyond Design: 10 Fundamental Rules of High-speed PCB Design, Part 3

12-13-2018

Planes are essential in today’s high-speed multilayer PCBs. Unfortunately, the number of power supplies required is increasing dramatically with IC complexity. Now, accounting for them all has become a real challenge. The high number of supplies generally leads to higher layer count substrates. In the past, we used to have more signal routing layers than planes; the opposite is now the case when the majority of stackup layers are reserved for power distribution. Although this increases the cost, it may be a godsend because it provides segregation of critical signals to avoid crosstalk and reduces radiation.

View Story

10 Fundamental Rules of High-speed PCB Design, Pt. 2

11-15-2018

In last month’s column, I introduced the 10 fundamental rules of high-speed PCB design. The first rule was to establish design constraints before commencing the design. This prime strategy sets constraints upfront based on pre-layout analyses or recommendations and guidelines and is integral to the design flow to maintain the established requirements. This month, I will elaborate on the importance of controlling the impedance and floor planning the placement based on connectivity.

View Story

Beyond Design: It’s a Material World

09-10-2018

Years ago, when clock frequencies were low and signal rise times were slow, selecting a dielectric material for your PCB was not difficult; we all just used FR-4. And we didn’t really care about the properties of the materials. However, with today’s multi-gigabit designs and their extremely fast rise times and tight margins, precise material selection is crucial to the performance of the product. Materials used for the fabrication of the multilayer PCB absorb high frequencies and reduce edge rates, and that loss in the transmission lines is a major cause of signal integrity issues. But we are not all designing cutting-edge boards and sometimes we tend to over-specify requirements that can lead to inflated production costs.

View Story

Beyond Design: Crosstalk Margins

08-22-2018

What is an acceptable level of crosstalk? That depends on the technology being used, and this level has changed quite dramatically over the years, going from TTL logic devices to today’s high-speed Gbps devices. In this month’s column, I will delve into the threshold of acceptable crosstalk and how to mitigate its impact on high-speed designs.

View Story

10 Fundamental Rules of High-Speed PCB Design, Pt. 1

08-06-2018

Over the years, I have focused on high-speed design, signal and power integrity, and EMC design techniques in a plethora of published technical articles—all of which have key points to consider and present a tremendous amount of information to absorb. In my next few columns, I will elaborate on ten of the most important considerations to embrace to achieve successful high-speed PCB designs that perform reliably to expectations.

View Story

DDR3/4 Fly-by Topology Termination and Routing

07-18-2018

DDR3/4 fly-by topology is similar to daisy chain or multi-drop topology, but it includes very short stubs to each memory device in the chain to reduce the reflections. The advantage of fly-by topology is that it supports higher-frequency operation and improves signal integrity and timing on heavily loaded signals. If you are employing high-frequency DDR4, then the bandwidth of the channel needs to be as high as possible. However, with today’s extremely fast edge rates, the sequencing of the stubs and the end termination, and the associate load, can make a measurable difference in signal quality. In this month’s column I will look at how best to route DDR3/4 fly-by topology.

View Story

Beyond Design: Common Symptoms of Common-Mode Radiation

06-27-2018

Electromagnetic radiation from digital circuits can occur as either differential mode or common mode. Differential mode is typically equal and opposite and therefore any radiating fields will cancel. Conversely, common-mode radiation from two coupled conductors is identical. It does not cancel, but rather reinforces.

View Story

Beyond Design: A Review of HyperLynx DRC

05-30-2018

There is an old saying, “You get what you pay for.” Does this mean that you should not expect too much from free software? After all, free software usually comes at a price: the results might be inaccurate, the software might be time-consuming to set up and use, and the tool might overlook issues that require a revision to mitigate. But HyperLynx DRC is the exception to the rule.

View Story

Beyond Design: AC/DC is Not Just a Rock Band

04-27-2018

Positioned at our usual table at the local pub in Melbourne, Australia one night in 1972, the boys and I laughed as a school boy, guitarist Angus Young, set up equipment and tuned a guitar. We assumed he was one of the roadies, and were gobsmacked when AC/DC unexpectedly fired up. This month, I will discuss AC coupling (or is it DC blocking?) of high-speed serial links as my taste in music has matured over the years.

View Story

The Target Impedance Approach to PDN Design

03-13-2018

Before you worry (or not) about post-layout PDN DC drop analysis, you first need to design an effective PDN pre-layout. Smart designers prevent problems before they arise, while others waste time and resources trying to fix the mess that they inadvertently created due to their lack of due diligence. Engineers and PCB designers need to visualize and understand how and where the currents flow.

View Story
Back

2009

Beyond Design: 10 Fundamental Rules of High-speed PCB Design, Part 3

12-13-2018

Planes are essential in today’s high-speed multilayer PCBs. Unfortunately, the number of power supplies required is increasing dramatically with IC complexity. Now, accounting for them all has become a real challenge. The high number of supplies generally leads to higher layer count substrates. In the past, we used to have more signal routing layers than planes; the opposite is now the case when the majority of stackup layers are reserved for power distribution. Although this increases the cost, it may be a godsend because it provides segregation of critical signals to avoid crosstalk and reduces radiation.

View Story

10 Fundamental Rules of High-speed PCB Design, Pt. 2

11-15-2018

In last month’s column, I introduced the 10 fundamental rules of high-speed PCB design. The first rule was to establish design constraints before commencing the design. This prime strategy sets constraints upfront based on pre-layout analyses or recommendations and guidelines and is integral to the design flow to maintain the established requirements. This month, I will elaborate on the importance of controlling the impedance and floor planning the placement based on connectivity.

View Story

Beyond Design: It’s a Material World

09-10-2018

Years ago, when clock frequencies were low and signal rise times were slow, selecting a dielectric material for your PCB was not difficult; we all just used FR-4. And we didn’t really care about the properties of the materials. However, with today’s multi-gigabit designs and their extremely fast rise times and tight margins, precise material selection is crucial to the performance of the product. Materials used for the fabrication of the multilayer PCB absorb high frequencies and reduce edge rates, and that loss in the transmission lines is a major cause of signal integrity issues. But we are not all designing cutting-edge boards and sometimes we tend to over-specify requirements that can lead to inflated production costs.

View Story

Beyond Design: Crosstalk Margins

08-22-2018

What is an acceptable level of crosstalk? That depends on the technology being used, and this level has changed quite dramatically over the years, going from TTL logic devices to today’s high-speed Gbps devices. In this month’s column, I will delve into the threshold of acceptable crosstalk and how to mitigate its impact on high-speed designs.

View Story

10 Fundamental Rules of High-Speed PCB Design, Pt. 1

08-06-2018

Over the years, I have focused on high-speed design, signal and power integrity, and EMC design techniques in a plethora of published technical articles—all of which have key points to consider and present a tremendous amount of information to absorb. In my next few columns, I will elaborate on ten of the most important considerations to embrace to achieve successful high-speed PCB designs that perform reliably to expectations.

View Story

DDR3/4 Fly-by Topology Termination and Routing

07-18-2018

DDR3/4 fly-by topology is similar to daisy chain or multi-drop topology, but it includes very short stubs to each memory device in the chain to reduce the reflections. The advantage of fly-by topology is that it supports higher-frequency operation and improves signal integrity and timing on heavily loaded signals. If you are employing high-frequency DDR4, then the bandwidth of the channel needs to be as high as possible. However, with today’s extremely fast edge rates, the sequencing of the stubs and the end termination, and the associate load, can make a measurable difference in signal quality. In this month’s column I will look at how best to route DDR3/4 fly-by topology.

View Story

Beyond Design: Common Symptoms of Common-Mode Radiation

06-27-2018

Electromagnetic radiation from digital circuits can occur as either differential mode or common mode. Differential mode is typically equal and opposite and therefore any radiating fields will cancel. Conversely, common-mode radiation from two coupled conductors is identical. It does not cancel, but rather reinforces.

View Story

Beyond Design: A Review of HyperLynx DRC

05-30-2018

There is an old saying, “You get what you pay for.” Does this mean that you should not expect too much from free software? After all, free software usually comes at a price: the results might be inaccurate, the software might be time-consuming to set up and use, and the tool might overlook issues that require a revision to mitigate. But HyperLynx DRC is the exception to the rule.

View Story

Beyond Design: AC/DC is Not Just a Rock Band

04-27-2018

Positioned at our usual table at the local pub in Melbourne, Australia one night in 1972, the boys and I laughed as a school boy, guitarist Angus Young, set up equipment and tuned a guitar. We assumed he was one of the roadies, and were gobsmacked when AC/DC unexpectedly fired up. This month, I will discuss AC coupling (or is it DC blocking?) of high-speed serial links as my taste in music has matured over the years.

View Story

The Target Impedance Approach to PDN Design

03-13-2018

Before you worry (or not) about post-layout PDN DC drop analysis, you first need to design an effective PDN pre-layout. Smart designers prevent problems before they arise, while others waste time and resources trying to fix the mess that they inadvertently created due to their lack of due diligence. Engineers and PCB designers need to visualize and understand how and where the currents flow.

View Story
Copyright © 2020 I-Connect007. All rights reserved.