Intel Opens Fab 9 in New Mexico
January 25, 2024 | IntelEstimated reading time: 2 minutes
Intel celebrated the opening of Fab 9, its cutting-edge factory in Rio Rancho, New Mexico. The milestone is part of Intel's previously announced $3.5 billion investment to equip its New Mexico operations for the manufacturing of advanced semiconductor packaging technologies, including Intel’s breakthrough 3D packaging technology, Foveros, which offers flexible options for combining multiple chips that are optimized for power, performance and cost.
“Today, we celebrate the opening of Intel’s first high-volume semiconductor operations and the only U.S. factory producing the world’s most advanced packaging solutions at scale. This cutting-edge technology sets Intel apart and gives our customers real advantages in performance, form factor and flexibility in design applications, all within a resilient supply chain. Congratulations to the New Mexico team, the entire Intel family, our suppliers, and contractor partners who collaborate and relentlessly push the boundaries of packaging innovation,” said Keyvan Esfarjani, Intel executive vice president and chief global operations officer.
Intel’s global factory network is a competitive advantage that enables product optimization, improved economies of scale and supply chain resilience. The Fab 9 and Fab 11x facilities in Rio Rancho represent the first operational site for mass production of Intel’s 3D advanced packaging technology. It is also Intel's first co-located high-volume advanced packaging site, marking an end-to-end manufacturing process that creates a more efficient supply chain from demand to final product.
Fab 9 will help fuel the next era of Intel’s innovation in advanced packaging technologies. As the semiconductor industry moves into the heterogeneous era that uses multiple “chiplets” in a package, advanced packaging technologies, such as Foveros and EMIB (embedded multi-die interconnect bridge), offer a faster and more cost-efficient path toward achieving 1 trillion transistors on a chip and extending Moore’s Law beyond 2030.
Foveros, Intel’s 3D advanced packaging technology, is a first-of-its-kind solution that enables the building of processors with compute tiles stacked vertically, rather than side-by-side. It also allows Intel and foundry customers to mix and match compute tiles to optimize cost and power efficiency.
"This investment by Intel underscores New Mexico’s continued dedication to bring manufacturing back home to America," said Gov. Michelle Lujan Grisham. "Intel continues to play a key role in the state’s technology landscape and strengthen our workforce, supporting thousands of New Mexico families.”
The $3.5 billion investment in Rio Rancho has created hundreds of high-tech Intel jobs, more than 3,000 construction jobs and an additional 3,500 jobs across the state.
Suggested Items
ZESTRON Academy Launches 2024 Advanced Packaging & Power Electronics Webinar Series
05/01/2024 | ZESTRONZESTRON, the leading global provider of high-precision cleaning products, services, and training solutions in the electronics manufacturing and semiconductor industries, proudly announces the launch of its highly anticipated webinar series on Advanced Packaging & Power Electronics, a webinar series on the latest innovations, cleaning, and corrosion challenges.
NextFlex Convenes the Hybrid Electronics Community at Binghamton University
05/01/2024 | NextFlexBinghamton University hosted the NextFlex hybrid electronics community on April 18 for a day of expert presentations, breakout sessions on technology and manufacturing topics, and networking.
Koh Young Extends Invitation to the 2024 IEEE Electronic Components and Technology Conference
04/30/2024 | Koh YoungKoh Young, the industry leader in True3D measurement-based inspection solutions, invites you to join us at the at the 2024 IEEE Electronic Components and Technology Conference from May 28-31, 2024, in Denver, Colorado at the Gaylord Rockies Resort & Convention Center.
iNEMI Packaging Tech Topic Series: Role of EDA in Advanced Semiconductor Packaging
04/26/2024 | iNEMIAdvanced semiconductor packaging with heterogenous integration has made on-package integration of multiple chips a crucial part of finding alternatives to transistor scaling. Historically, EDA tools for front-end and back-end design have evolved separately; however, design complexity and the increased number of die-to-die or die-to-substrate interconnections has led to the need for EDA tools that can support integration of overall design planning, implementation, and system analysis in a single cockpit.
IDTechEx Explores the Role of 3D Cu-Cu Hybrid Bonding in Powering Future HPC and AI Products
04/18/2024 | PRNewswireSemiconductor packaging has evolved from traditional 1D PCB levels to cutting-edge 3D hybrid bonding at the wafer level, achieving interconnecting pitches as small as single micrometers and over 1000 GB/s bandwidth. Key parameters, including Power, Performance, Area, and Cost, are crucial considerations