Beyond Design: Pre-Layout Simulation

Reading time ( words)

Figure 10 highlights the routed MA0 Address signal starting at the processor (U1) – through a series terminator, then on to U5, U4, U3 and U2 – finally being pulled up by R18 to VTT. Fortunately, source synchronous busses have a unique immunity to crosstalk, provided that the ringing has settled by the sample and hold times.                                    

Figure 10. Multi-drop address line, MA0.

The post-layout simulation of the address signals (Figure 11), confirms that the correct selection of topology and termination strategies was made. The fact that the prototype board worked the first time, when tested, is also a very good indication.

Figure 11. Post-layout address simulation results (MA0).

The DDR2 differential clock(s) should also be routed to the exact same length, and daisy chained, just as the address bus should be. The time or skew between these should fall within specs. This brings us to the next point in pre-layout simulation: floor planning. Obviously, once you have established the individual lengths of the interconnects – with or without termination – you have the distance required to place the memory chips relative to the processor. The processor should be placed in the center of the board, whenever possible, to aid fanout and routing to peripheral devices.

Figure 12. T-section routing of DDR2 address signals.

Figure 12 shows the address signals routed in a T section. The signals start at the processor on the right, and route down at 45 degrees before splitting off to the memory chips above and below. In this case, the delay of the 45-degree sections should be identical, and the delay on each of the branches should be identical – quite a challenge for the novice PCB designer to tackle!

In a star topology, all signals emanate from a central node. The electrical delay for each leg of the star should be identical, and the loads should be the same—otherwise a series terminator can be used at the start of each leg to balance the delay and loading.

By utilizing a PCB board-level simulation service, you can be assured that your PCB will be reliable and manufacturable, will conform to specifications, as well as passing the relevant compliance tests. Saving one board spin or prototype can easily cover the cost of such a service, and the peace of mind – in terms of reliability – is priceless.

Points to remember:

  • Problems can be identified and prevented using pre-layout simulation
  • Select the optimal topology style for signal integrity, timing, crosstalk, and EMC
  • Unterminated high-speed traces should be less than 1/10 the driver rise time
  • Closely match the data signals and data mask to the associated strobes, and the address, command and control signals to the clocks
  • Pre-layout simulation allows you to experiment with termination strategies
  • The processor should be placed in the center of the board to aid fanout and routing to peripheral devices
  • Establish routing constraints based on the pre-layout simulation
  • Return paths should be checked to ensure there are no split planes or obstacles to impede the return current


The ICD Stackup Planner with Field Solver Technology can be downloaded from

Barry Olney is managing director of In-Circuit Design Pty Ltd. (ICD), Australia, a PCB design service bureau and board level simulation specialist. Among others, ICD was awarded “Top 2005 Asian Distributor Marketing,” and “Top 2005 Worldwide Distributor Marketing” by Mentor Graphics, Board System Division. For more information, contact Olney at +61 4123 14441 or by e-mail:



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